This application claims priority to Korean Patent Application No. 2004-0033808, filed on May 13, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to characterization of semiconductor devices, and more particularly, to having separate signal transmission paths for normal operation of the semiconductor device and for parameter measurement of the semiconductor device.
2. Description of the Related Art
A scattering (S) parameter, measured for a semiconductor device such as a memory device, is the ratio of an output signal to an input signal in a frequency domain. The S parameter is comprised of an input reflection coefficient such as S11 and a transmission coefficient such as S21, as known to one of ordinary skill in the art. The S parameter is widely used to determine characteristics (such as an RLC value) of a system operating at radio frequency. U.S. Pat. No. 6,300,775 discloses a network analyzer which is an example of an S parameter measurement instrument.
FIG. 1 schematically shows a conventional memory system 100. The conventional memory system 100 includes a memory controller 110, a bus channel 120, memory modules 130 and 140, and memory slots 150 and 160.
The memory controller 110 controls the memory system 100 so that data is input/output into/from the memory modules 130 and 140 via the bus channel 120. The memory controller 110 is also referred to as a chipset.
The bus channel 120 includes a data bus and a control bus. The control bus transmits a control signal such as a clock signal or an address signal used for controlling data transmission via the data bus.
The memory modules 130 and 140 are installed (or inserted) in (or into) the memory slots 150 and 160, respectively, and are connected to the memory controller 110 via the bus channel 120. Referring to FIG. 1, the memory modules 130 and 140 each are dual in-line memory modules (DiMM) having dual ranks [R0, R1] and [R2, R3], respectively. However, each of the memory modules 130 and 140 may be a DiMM having a single rank. Each rank of a memory module includes at least one semiconductor memory device (such as a DRAM (dynamic random access memory) device).
Each of the memory modules 130 and 140 includes on die termination (ODT) circuits. Each semiconductor device of the memory modules 130 and 140 includes a respective one of the ODT circuits [131, 132] and [141, 142]. Each ODT circuit is a termination matching circuit installed inside of a respective semiconductor memory device for preventing distortion of data caused by signal reflection during normal operation (such as a read/write operation) of the semiconductor memory devices. Each of the ODT circuits [131, 132] and [141, 142] is connected to a DQ pin or a DQ port of the respective semiconductor memory device.
The operation of the ODT circuits [131, 132] and [141, 142] is now described. Assume that the semiconductor memory devices [R0, R1] of the first memory module 130 perform a write operation or a read operation. In that case, the ODT circuits [141, 142] of the second memory module 140 are turned on (or activated) in response to a first termination control signal transmitted via the bus channel 120 for impedance matching with the bus channel 120. Additionally in that case, the ODT circuits [131, 132] of the first memory module 130 are turned off (or deactivated) in response to a second termination control signal transmitted via the bus channel 120. The first and second termination control signals are generated by the memory controller 110.
On the other hand, assume that the semiconductor memory devices [R2, R3] of the second memory module 140 perform a write operation or a read operation. In that case, the ODT circuits [131, 132] of the first memory module 130 are turned on (or activated) in response to the first termination control signal transmitted via the bus channel 120 for impedance matching with the bus channel 120. Additionally in that case, the ODT circuits [141, 142] of the second memory module 140 are turned off (or deactivated) in response to the second termination control signal transmitted via the bus channel 120.
FIG. 2 is a circuit diagram showing an example of an ODT circuit 131 of FIG. 1. The ODT circuit 131 of FIG. 2 is a center tap termination (CTT) type including switches SW1 and SW2 and termination resistors RT1 and RT2. The other ODT circuits 132, 141, and 142 of FIG. 1 are implemented similarly as the ODT circuit 131 of FIG. 2.
Each of the switches SW1 and SW2 may be implemented as a MOS transistor. Each of the switches SW1 and SW2 turns on the ODT circuit 131 in response to the activation of a first termination control signal ODT_C (i.e., when the ODT_C signal has a logical high state). That is, the switches SW1 and SW2 turn on within the ODT circuit 131 to couple a power supply voltage VDDQ to a first termination resistor RT1 and to couple a ground voltage VSSQ to a second termination resistor RT2.
When the switches SW1 and SW2 are closed for such coupling of the voltages VDDQ and VSSQ to the termination resistors RT1 and RT2, the ODT circuit 131 is deemed to be turned on. On the other hand, when the switches SW1 and SW2 are opened such that the voltages VDDQ and VSSQ are disconnected from the termination resistors RT1 and RT2, the ODT circuit 131 is deemed to be turned off.
The termination resistors RT1 and RT2 have the same resistance. The termination resistors RT1 and RT2 are connected together at a node A that is also connected to a DQ pin of the respective semiconductor memory device having the ODT circuit 131 therein.
A scattering parameter such as the S11 parameter is desired to be measured by a network analyzer (which is an example tester) from the DQ pin of the semiconductor memory device. Such a scattering parameter is used for designing the bus channel 120 to which the memory modules 130 and 140 and the memory controller 110 are coupled.
Conventionally, the S11 parameter is measured in a state where the ODT circuit of the semiconductor memory device is turned off (i.e., the switches SW1 and SW2 are turned off in FIG. 2) after power is supplied to the semiconductor memory device. However, the semiconductor memory devices in FIG. 1 perform normal operations with the ODT circuits being turned on or off. Thus, the S11 parameter measured in the conventional manner does not accurately characterize the bus channel 120 during normal operation of the semiconductor memory devices.
With such inaccurate characterization of the bus channel 120, integrity of the signals transmitted within the memory system 100 is compromised, especially at higher operating frequencies of the memory system 100.
Thus, a mechanism is desired for more accurately measuring a parameter from a DQ pin of the memory device with control of the ODT circuit coupled to the DQ pin.